A method of regulating a voltage difference between a word line and a digit line of a load less, four transistor memory cell

ABSTRACT

The present invention is a current-mirror-based bias generator for a load less four transistor SRAM as well as associated methods of controlling or modifying the current conducted by the access transistors of such an SRAM. The present invention may be thought of as an adjustable temperature coefficient, bias generator that references, via a current mirror, a reference bank of SRAM cells. The bank of reference cells provides an indication of the necessary conduction characteristics (e.g., gate to source voltage) of the access transistors under various conditions. By applying a bias voltage to the word line the desired current is sourced from the digit line. The bank of reference SRAM cells inherently compensates for process variations. The adjustable temperature coefficient bias generator allows the current sourced by the digit lines to vary greatly as a result of temperature variations. Thus, the present invention compensates for both process variations and temperature variations.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates generally to static-random-access-memory(SRAM) devices and, more particularly, to SRAM's utilizing a fourtransistor design.

[0003] 2. Description of the Background

[0004] To meet customer demand for smaller and more power efficientintegrated circuits (ICs), manufacturers are designing newer ICs thatoperate with lower supply voltages and that include smaller internalsubcircuits such as memory cells. Many ICs, such as memory circuits orother circuits such as microprocessors that include onboard memory,include arrays of SRAM cells for data storage. SRAM cells are popularbecause they operate at a higher speed than dynamic-random-access-memory(DRAM) cells, which must be periodically refreshed.

[0005]FIG. 1 is a circuit diagram of a conventional 6-transistor (6-T)SRAM cell 10, which can operate at a relatively low supply voltage, forexample 1.5V-3.3V, but which is relatively large. A pair of NMOS accesstransistors 12 and 14 allow complementary bit values D and {overscore(D)} on digit lines 16 and 18, respectively, to be read from and to bewritten to a storage circuit 20 of the cell 10. The storage circuit 20includes NMOS pull-down transistors 22 and 26, which are coupled in apositive-feedback configuration with PMOS pull-up transistors 24 and 28,respectively. Nodes A and B are the complementary inputs/outputs of thestorage circuit 20, and the respective complementary logic values atthese nodes represent the state of the cell 10. For example, when thenode A is at logic 1 and the node B is at logic 0, then the cell 10 isstoring a logic 1. Conversely, when the node A is at logic 0 and thenode B is at logic 1, then the cell 10 is storing a logic 0. Thus, thecell 10 is bistable, i.e., the cell 10 can have one of two stablestates, logic 1 or logic 0.

[0006] In operation during a read of the cell 10, a word-line WL, whichis coupled to the gates of the transistors 12 and 14, is driven to avoltage approximately equal to Vcc to activate the transistors 12 and14. For example purposes, assume that Vcc=logic 1=5V and Vss=logic 0=0V,and that at the beginning of the read, the cell 10 is storing a logic 0such that the voltage level at the node A is 0V and the voltage level atthe node B is 5V. Also, assume that before the read cycle, the digitlines 16 and 18 are equilibrated to approximately Vcc-Vt. Therefore, theNMOS transistor 12 couples the node A to the digit line 16, and the NMOStransistor 14 couples the node B to the digit line 18. For example,assume that the threshold voltages of the transistors 12 and 14 are both1V, then the transistor 14 couples a maximum of 4V from the digit line18 to the node B. The transistor 12, however, couples the digit line 16to the node A, which pulls down the voltage on the digit line 16 enough(for example, 100-500 millivolts) to cause a sense amp (not shown)coupled to the lines 16 and 18 to read the cell 10 as storing a logic 0.

[0007] In operation during a write, for example, of a logic 1 to thecell 10, and making the same assumptions as discussed above for theread, the transistors 12 and 14 are activated as discussed above, andlogic 1 is driven onto the digit line 16 and a logic 0 is driven ontothe digit line 18. Thus, the transistor 12 couples 4V (the 5V on thedigit line 16 minus the 1V threshold of the transistor 12) to the nodeA, and the transistor 14 couples 0V from the digit line 18 to the nodeB. The low voltage on the node B turns off the NMOS transistor 26, andturns on the PMOS transistor 28. Thus, the inactive NMOS transistor 26allows the PMOS transistor 28 to pull the node A up to 5V. This highvoltage on the node A turns on the NMOS transistor 22 and turns off thePMOS transistor 24, thus allowing the NMOS transistor 22 to reinforcethe logic 0 on the node B. Likewise, if the voltage written to the nodeB is 4V and that written to the node A is 0V, the positive-feedbackconfiguration ensures that the cell 10 will store a logic 0.

[0008] Because the PMOS transistors 24 and 28 have low on resistances(typically on the order of a few kilohms), they can pull the respectivenodes A and B virtually all the way up to Vcc often in less than 10nanoseconds (ns), and thus render the cell 10 relatively stable andallow the cell 10 to operate at a low supply voltage as discussed above.But unfortunately, the transistors 26 and 28 cause the cell 10 to beapproximately 30%-40% larger than a 4-transistor (4-T) SRAM cell, whichis discussed next.

[0009]FIG. 2 is a circuit diagram of a conventional 4-T SRAM cell 30,where elements common to FIGS. 1 and 2 are referenced with likenumerals. A major difference between the 6-T cell 10 and the 4-T cell 30is that the PMOS pull-up transistors 24 and 28 of the 6-T cell 10 arereplaced with conventional passive loads 32 and 34, respectively. Forexample, the loads 32 and 34 are often polysilicon resistors. Otherwisethe topologies of the 6-T cell 10 and the 4-T cell 30 are the same.Furthermore, the 4-T cell 30 operates similarly to the 6-T cell 10.Because the loads 32 and 34 are usually built in another level above theaccess transistors 12 and 14 and the NMOS pull-down transistors 22 and26, the 4-T cell 30 usually occupies much less area than the 6-T cell10.

[0010] Additional, complex steps are required to form the load elements32 and 34 such that 4-T cells present the usual complexity versus costtradeoff. The high resistance values of the loads 32 and 34 cansubstantially lower the stability margin of the cell 30 as compared withthe cell 10. Thus, under certain conditions, the cell 30 caninadvertently become monostable or read unstable instead of bistable.Also, the cell 30 consumes more power than the cell 20 because there isalways current flowing from Vcc to Vss through either the load 32 andthe NMOS transistor 26 or the load 34 and the NMOS transistor 22. Incontrast, current flow from Vcc to Vss in the cell 20 is always blockedby one of the NMOS/PMOS transistor pairs 22/24 and 26/28. Efforts toeliminate load elements 32 and 34 have lead to the development of aload-less four transistor SRAM cell as shown in FIG. 3.

[0011]FIG. 3 is a circuit diagram of a conventional load-less 4-T SRAMcell, where elements common to FIGS. 2 and 3 are referenced with likenumerals. The difference between the load-less cell 36 and the cell 30is the elimination of load elements 32 and 34 and the replacement ofNMOS transistors 12 and 14 with PMOS transistors 38 and 40,respectively.

[0012] With the load-less 4-T SRAM cell of FIG. 3, like all SRAM cells,leakage currents and/or subthreshold currents are generated bytransistors 22 and 26 when in the off state, and one will always be inthe off state. To prevent the cell 36 from spontaneously changing state,the transistors 38 and 40 must source sufficient load current from thedigit lines 16 and 18, respectively, to offset the leakage andsubthreshold currents. The needed load current can vary over many ordersof magnitude due to temperature and process variations. However, theload current cannot be too large because the cumulative (along the digitlines 16 and 18) load current needs to be significantly less than thecell current for proper noise margin for proper operation of the senseamps.

[0013] Wide temperature variations resulting from cold-data retentiontesting and burn-in testing are also causes of wide variations inleakage and subthreshold currents, thereby causing wide variations inthe load current that must be sourced by transistors 38 and 40. Suchtesting, coupled with normal process variations, sense amp marginrequirements, as well as yield requirements (e.g., read/write stabilityrequirements, power consumption requirements, etc.) have made themanufacturing of load-less 4-T SRAM's a difficult matter.

SUMMARY OF THE PRESENT INVENTION

[0014] The present invention is directed generally to a bias generatorused in conjunction with one of the word line or digit line to set thedesired level of load current as a function of temperature (or testbeing performed) to satisfy the simultaneous constraints of yield, senseamp margin, and load current even during cold-data retention testing orburn-in.

[0015] The present invention is also directed to a method of modifyingthe level of current conducted by the access transistors of a load-less,four transistor memory cell when the access transistors are in an offstate. The method is comprised of the step of generating a temperaturedependent bias voltage and connecting that bias voltage to the gateterminals of the access transistors.

[0016] The present invention is also directed to a current-mirror-basedbias generator for a load-less four transistor SRAM as well asassociated methods of controlling or modifying the current conducted bythe access transistors of such an SRAM. The present invention may bethought of as an adjustable temperature coefficient, bias generator thatreferences, via a current mirror, a reference bank of SRAM cells. Thebank of reference cells provides an indication of the necessaryconduction characteristics (e.g., gate to source voltage) of the accesstransistors under various conditions. By applying a bias voltage to theword line the desired current is sourced from the digit line. The bankof reference SRAM cells inherently compensates for process variations.The adjustable temperature coefficient bias generator allows the currentsourced by the digit lines to vary greatly as a result of temperaturevariations. Thus, the present invention compensates for both processvariations and temperature variations. Those benefits, and others, willbecome apparent from the description of the preferred embodimenthereinbelow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] For the present invention to be easily understood and readilypracticed, the invention will now be described for purposes ofillustration and not limitation, in conjunction with the followingfigures wherein:

[0018]FIG. 1 is a circuit diagram of a conventional 6-T SRAM cell;

[0019]FIG. 2 is a circuit diagram of a conventional 4-T SRAM cell;

[0020]FIG. 3 is a circuit diagram of a conventional load-less 4-T SRAMcell;

[0021]FIG. 4 is a circuit diagram of a load-less 4-T SRAM cell inconjunction with a bias generator constructed according to the teachingsof the present invention;

[0022]FIG. 5 is a block diagram of a portion of an array of 4-T SRAMcells incorporating the bias generator of the present invention;

[0023]FIG. 6 is a block diagram of a load-less 4-T SRAM incorporatingthe bias generator of the present invention;

[0024]FIG. 7 is a block diagram of a computer system that includes the4-T SRAM of FIG. 6;

[0025]FIG. 8 illustrates another embodiment of the present invention;and

[0026]FIG. 9 is a block diagram illustrating how the bias voltage on theglobal bus can be forced to any value.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027]FIG. 4 is a circuit diagram of a load-less 4 transistor SRAM cell36 in conjunction with a bias generator 42 constructed according to theteachings of the present invention. The cell 36 illustrated in FIG. 4 isidentical to the cell 36 illustrated in FIG. 3. The bias generator 42 iscomprised of a bank of transistors 44 connected in parallel with eachother and connected in series with a temperature dependent constantcurrent source 46. The bank of transistors 44 is fabricated at the sametime, and in the same manner, as access transistors 38 and 40. In thatmanner, the voltage drop from the gate terminal to the source terminalof each of the transistors 44 should be substantially the same as thegate to source terminal drop of access transistors 38 and 40. Thus, thevoltage drop across the gate and source terminals of each of thetransistors 44 is representative of the voltage drop across the gate andsource terminals of the transistors 38 and 40. As an alternative toseparately fabricating the bank of transistors 44, a bank of cells 36could carry additional wiring so that the gate to source voltage of theaccess transistors 38 and 40 can be sensed.

[0028] Returning to the bias generator 42, the current source 46 may beconstructed using any known techniques which provide a temperaturedependent constant current source. The constant current source willproduce one value of current under, for example, cold data-retentiontest conditions, and another value of current under burn-in testconditions. Thus, for each value of current produced by the temperaturedependent constant current source 46, a different voltage drop acrossthe gate and source terminals of the transistors 44 is produced. Thatvoltage drop is averaged and sensed by an operational amplifier 48.Although the bias generator 42 would operate if only one transistor forthe bank of transistors 44 was provided, by providing a plurality oftransistors within bank 44, a voltage drop which is more representativeof the voltage drop experienced in the cells is produced. The voltagedrop sensed by the operational amplifier 48 may then be applied to theword line which, as seen in the figure, is connected to the gateterminals of the access transistors 38 and 40. Thus, when the cell 36 isin the off-state, i.e., transistors 38 and 40 are nonconductive, thebias voltage applied by the operational amplifier 48 may be used tocontrol the conduction characteristics of the access transistors 38 and40 so as to enable the transistors 38 and 40 to source current from thedigit lines 16 and 18. Because the bias voltage is directly related tothe current which is produced by the constant current source 46, and thecurrent is temperature dependent, the bias voltage is also temperaturedependent. Thus, the conduction characteristics of the accesstransistors 38 and 40 are controlled according to the temperature suchthat the current required by the cell 36, for a given temperature, maybe properly sourced.

[0029] The temperature dependent constant current source may receiveinputs from a programmable device 45. The programmable device 45 maycontain laser trimmable devices, fuses, or antifuses, which allowmanipulation of a value adjust signal (VA) and a temperature coefficientadjust signal (TCA) to provide some degree of control over the biasvoltage post fabrication.

[0030]FIG. 5 is a block diagram of a portion of an array 50 of fourtransistor SRAM cells 36 incorporating the bias generator 42 of thepresent invention. In FIG. 5, a plurality of digit lines D, {overscore(D)}, and a plurality of word lines WL1-WL4 are used to interconnectindividual memory cells 36. The bias generator 42, constructed as shownin FIG. 4, globally provides the bias voltage to the array via globalbus 54. The bias generator 42 may be coupled to each of the word linesWL1-WL4 through a transistor pair 52. Each transistor pair 52 iscomprised of a PMOS and an NMOS transistor. The PMOS transistor may beconnected between the bias generator 42 and a word line, e.g., WL1. TheNMOS transistor may be connected between the word line, e.g. WL1, andground. Each transistor is responsive to a word line select signal, e.g.Sel WL1.

[0031] In operation, only one word line will be active at a time. Forword lines not selected, the NMOS transistor of the transistor pair 52will be off while the PMOS transistor will be on thereby coupling thebias voltage to each of the non-selected word lines. When a word line isselected, e.g., WL1, the word line select signal, e.g., Sel WL1, willcause the transistors to change state. Specifically, the NMOS transistorwill turn on connecting the word line to ground thereby rendering theword line active while the PMOS transistor will turn off thereby endingthe application of the bias voltage to the active word line.

[0032] To provide a particular voltage for a test mode, a voltage source56 may be coupled to the global bus 54 through a transistor 58. Thevoltage source may be capable of outputting different voltages dependingupon one or more control signals 60. Upon assertion of the signal{overscore (Tm)}, the bias generator 42 is disabled and the output ofthe voltage source 56 is applied to the global bus 54. Voltage source 56may include a constant current source as well as a laser trimmabledevice, fuses, or antifuses as discussed above for the purpose of givingthe manufacturer some degree of control over the voltage(s) produced bythe voltage source 56 post fabrication.

[0033] Another way to implement the functionality described in theprevious paragraph is through the use of more than one constant currentsource in the bias generator 42 as shown in FIG. 8. For example, asecond constant current source 46′ could be operatively connectedthrough a switch 66 to the remainder of the circuit for producing avoltage input to op amp 48. The constant current source 46′ isresponsive to a particular test mode instead of being responsive to thetemperature.

[0034] Another embodiment of the present invention is illustrated inFIG. 9. In FIG. 9, a pad 62 is connected to the global bus 54 through atransistor 64. Whenever the signal {overscore (Tm)}-force is asserted,the bias generator 42 is disabled and the voltage available at the pad62 is placed on the global bus 54. Thus, the voltage on global bus 54may be forced to any value. When the signal {overscore (Tm)}-measure isasserted, the voltage on bus 54 can be measured at pad 62. Thisfunctionality is useful for characterization purposes as well as yieldand reliability screening.

[0035]FIG. 6 is a block diagram of a memory circuit 70 which can includecells 36 and the bias generator 42 as previously described. In oneembodiment, the memory circuit 70 may be a synchronous SRAM.

[0036] The memory circuit 70 includes an address register 72, whichreceives an address from an ADDRESS bus (not shown). A control logiccircuit 74 receives a clock (CLK) signal, and receives enable and writesignals on a COMMAND bus (not shown), and communicates with the othercircuits of the memory circuit 70. A burst counter 75 causes the memorycircuit 70 to operate in a burst address mode in response to a MODEsignal.

[0037] During a write cycle, write driver circuitry 76 writes date to amemory array 78. The array 78 is the component of the memory circuit 70that can include the cells 36 and bias generator 42. The array 78 alsoincludes an address decoder 80 for decoding the address from the addressregister 72. Alternately, the address decoder 80 may be separate fromthe array 78.

[0038] During a read cycle, sense amplifiers 82 amplify and provide thedata read from the array 78 to a data input/output (I/O) circuit 84. TheI/O circuit 84 includes output circuits 86, which provide data from thesense amplifiers 82 to a DATA bus (not shown) during a read cycle. TheI/O circuit 84 also includes input circuits 88, which provide data fromthe DATA bus to the write drivers 76 during a write cycle. The input andoutput circuits 88 and 86, respectively, may include conventionalregisters and buffers. Furthermore, the combination of the write drivercircuitry 76 and the sense amplifiers 82 can be referred to asread/write circuitry. The various components shown in FIG. 6, with theexception of the array 78, constitute a plurality of components forreading information out of, and writing information into, the array 80.

[0039]FIG. 7 is a block diagram of an electronic system 90, such as acomputer system, that incorporates the memory circuit 70 of FIG. 6. Thesystem 90 includes computer circuitry 92 for performing computerfunctions, such as executing software to perform desired calculationsand tasks. The circuitry 92 typically includes a processor 94 and thememory circuit 70, which is coupled to the processor 94. One or moreinput devices 96, such as a keyboard or a mouse, are coupled to thecomputer circuitry 92 and allow an operator (not shown) to manuallyinput data thereto. One or more output devices 98 are coupled to thecomputer circuitry 92 to provide to the operator data generated by thecomputer circuitry 92. Examples of such output devices 98 include aprinter and a video display unit. One or more data-storage devices 100are coupled to the computer circuitry 92 to store data on or retrievedata form external storage media (not shown). Examples of the storagedevices 100 and the corresponding storage media include drives thataccept hard and floppy disks, tape cassettes, and compact disk read-onlymemories (CD-ROMs). Typically, the computer circuitry 92 includesaddress, data, and command buses and a clock line that are respectivelycoupled to the ADDRESS, DATA and COMMAND buses, and the CLK line of thememory circuit 70.

[0040] The present invention is also directed to a method of controllingthe load current in a load-less four transistor memory cell. The methodis comprised of the step of providing a temperature dependent biasvoltage to one of the word line or the digit line. The providing stepmay be comprised of the steps of generating a temperature dependentconstant current, generating a voltage drop across two terminals of atransistor representative of the transistors in the memory cell with thetemperature dependent constant current, and sensing the voltage drop toproduce the bias voltage. The voltage drop may be generated across aplurality of transistors to provide an average value for the voltagedrop. By connecting or applying the bias voltage to one of the word lineor digit line, the conduction of the access transistors of the memorycell may be controlled. However, because of the different function whichthe digit line performs in the context of a memory cell, it isconsidered preferable to apply the bias voltage to the word line. Thepresent invention is also directed to a method of regulating a voltagedifference between the word line and the digit line in a load-less fourtransistor memory cell by applying a temperature dependent bias voltageto one of the word line or the digit line.

[0041] While the present invention has been described in conjunctionwith preferred embodiments thereof, those of ordinary skill in the artwill recognize that many modifications and variations are possible. Forexample, the type of transistors used to construct the cell may bevaried such that the terminals in issue need not be the gate and sourceterminals. As previously mentioned, the same result can be achieved byvarying the voltage on the digit line or, alternatively, controlling thevoltage differential between the word line and the digit line. Theforegoing disclosure and the following claims are intended to encompassall such modifications and variations.

What is claimed is:
 1. A voltage generator for providing a bias voltageto a word line, comprising: a constant current source for producingdifferent levels of current in response to different conditions; atleast one transistor connected in series with said constant currentsource; an amplifier responsive to a voltage across two terminals ofsaid transistor; and a drive circuit responsive to said amplifier forbiasing a word line.
 2. The voltage generator of claim 1 wherein saidconstant current source is responsive to different temperatureconditions.
 3. The voltage generator of claim 1 additionally comprisinga laser trimmable device connected with said constant current source. 4.The voltage generator of claim 1 additionally comprising a plurality offuses connected with said constant current source.
 5. The voltagegenerator of claim 1 additionally comprising a plurality of antifusesconnected with said constant current source.
 6. A temperature dependentvoltage generator, comprising: a temperature dependent constant currentsource for producing different levels of current in response todifferent temperatures; at least one transistor connected in series withsaid constant current source; an amplifier responsive to a voltageacross certain terminals of said transistor; and a drive circuitresponsive to said amplifier for providing a voltage.
 7. The voltagegenerator of claim 6 wherein said amplifier is responsive to a voltageacross a gate terminal and a source terminal.
 8. The voltage generatorof claim 6 additionally comprising means connected with said constantcurrent source for controlling the voltage post fabrication.
 9. Atemperature compensated bias generator for use with an array ofload-less four transistor memory cells interconnected by bit lines andword lines, said bias generator comprising: a temperature dependentconstant current source; a plurality of transistors connected inparallel with one another and in series with said constant currentsource; an amplifier responsive to an average voltage across twoterminals of said plurality of transistors; and a drive circuitresponsive to said amplifier for providing a bias voltage.
 10. The biasgenerator of claim 9 wherein said average voltage across two terminalsincludes the average voltage across a gate terminal and a sourceterminal of each transistor in said plurality of transistors.
 11. A biasgenerator, comprising: a temperature dependent constant current source,a constant current source, a circuit for producing a bias voltage inresponse to one of said current sources; and a switch for connecting oneof said constant current sources to said circuit.
 12. The bias generatorof claim 11 wherein said switch is responsive to a test mode signal. 13.The bias generator of claim 11 additionally comprising a laser trimmabledevice connected to said temperature dependent constant current source.14. The bias generator of claim 11 additionally comprising a pluralityof fuses connected to said temperature dependent constant currentsource.
 15. The bias generator of claim 11 additionally comprising aplurality of antifuses connected to said temperature dependent constantcurrent source.
 16. The bias generator of claim 11 additionallycomprising a laser trimmable device connected to said constant currentsource.
 17. The bias generator of claim 11 additionally comprising aplurality of fuses connected to said constant current source.
 18. Thebias generator of claim 11 additionally comprising a plurality ofantifuses connected to said constant current source.
 19. A combinationcomprising: an array of memory cells each comprised of not more thanfour transistors; a plurality of digit lines and word linesinterconnecting said array of memory cells; and a bias generator forproducing different levels of current in response to differentconditions, said bias generator for providing a bias voltage to one ofsaid word lines and digit lines.
 20. The combination of claim 19 whereinsaid bias generator is responsive to temperature.
 21. The combination ofclaim 19 wherein said bias generator is responsive to different testmodes.
 22. A combination comprising: an array of memory cells eachcomprised of not more than four transistors; a plurality of digit linesand word lines interconnecting said array of memory cells; a biasgenerator for providing a temperature sensitive bias voltage to one ofsaid word lines and digit lines in response to a control signal; avoltage source for providing a fixed bias voltage to one of said wordlines and digit lines; and a switch responsive to the control signal forconnecting said voltage source to one of said word lines and digit lineswhen the control signal disconnects said bias generator.
 23. Acombination comprising: an array of memory cells each comprised of notmore than four transistors; a plurality of digit lines and word linesinterconnecting said array of memory cells; a bias generator forproviding a temperature sensitive bias voltage to one of said word linesand digit lines; an input/output pad; and a switch responsive to thecontrol signal for selectively connecting said pad to one of said wordlines and digit lines in response to a control signal.
 24. A staticrandom access memory, comprising: an array of memory cells eachcomprised of not more than four transistors; a plurality of digit linesand word lines interconnecting said array of memory cells; a biasgenerator for producing different levels of current in response todifferent conditions, said bias generator for providing a bias voltageto one of said word lines and digit lines; and a plurality of peripheraldevices, responsive to said digit lines and said word lines forcontrolling the input of information to, and output of information from,said array of memory cells.
 25. The memory of claim 24 wherein said biasgenerator is responsive to temperature.
 26. The memory of claim 24wherein said bias generator is responsive to different test modes.
 27. Asystem, comprising: a microprocessor; a plurality of memory devices incommunication with said microprocessor, each of said memory devicescomprising: an array of memory cells each comprised of not more thanfour transistors; a plurality of digit lines and word linesinterconnecting said array of memory cells; a bias generator forproducing different levels of current in response to differentconditions, said bias generator for providing a bias voltage to one ofsaid word lines and digit lines; and a plurality of peripheral devices,responsive to said digit lines and said word lines for controlling theinput of information to, and output of information from, said array ofmemory cells.
 28. A method of controlling the load current in a loadless four transistor memory cell, comprising: providing a temperaturedependent bias voltage to one of the word line and the digit line. 29.The method of claim 28 wherein said step of providing a bias voltageincludes the steps of: generating a temperature dependent constantcurrent; generating a voltage drop across two terminals of a transistorrepresentative of the access transistors in the memory cell with saidtemperature dependent constant current; and sensing said voltage drop toproduce the bias voltage.
 30. The method of claim 29 additionalcomprising the steps of generating a plurality of voltage drops acrosstwo terminals of a plurality of transistors representative of the accesstransistors in the memory cell with said temperature dependent constantcurrent, and averaging said voltage drops before said sensing step. 31.A method of controlling the conduction of the access transistors of aload-less, four transistor memory cell, comprising: applying atemperature dependent bias voltage to control terminals of the accesstransistors.
 32. The method of claim 31 additionally comprising thesteps of: generating a temperature dependent constant current;generating a voltage drop across two terminals of a transistorrepresentative of the access transistors with said temperature dependentconstant current; and sensing said voltage drop to produce thetemperature dependent bias voltage.
 33. The method of claim 32additionally comprising the steps of generating a plurality of voltagedrops across two terminals of a plurality of transistors representativeof the access transistors in the memory cell with said temperaturedependent constant current, and averaging said voltage drops before saidamplifying step.
 34. A method of modifying the level of currentconducted by the access transistors of a load-less, four transistormemory cell when said transistors are in an off-state, comprising:generating a temperature dependent bias voltage; providing a test modebias voltage; and connecting one of said temperature dependent biasvoltage and test mode bias voltage to control terminals of the accesstransistors.
 35. The method of claim 34 wherein said step of generatinga temperature dependent bias voltage includes the steps of: generating atemperature dependent constant current; and sensing a voltage dropacross two terminals of a transistor representative of the accesstransistors as a result of the application of said temperature dependentconstant current to generate the temperature dependent bias voltage. 36.The method of claim 35 additionally comprising the steps of generating aplurality of voltage drops across two terminals of a plurality oftransistors representative of the transistors in the memory cell withsaid temperature dependent constant current, and averaging said voltagedrops.
 37. A method of regulating a voltage difference between the wordline and digit line of a load-less four transistor memory cell,comprising: applying one of a temperature dependent bias voltage and atest mode bias voltage to one of the word line and digit line.
 38. Themethod of claim 37 additionally comprising the step of generating saidtest mode bias voltage.
 39. The method of claim 37 wherein said testmode bias voltage is applied from an input/output pad.
 40. The method ofclaim 37 additionally comprising the steps of: generating a temperaturedependent constant current; generating a voltage drop across twoterminals of a transistor representative of the transistors in thememory cell with said temperature dependent constant current; andsensing said voltage drop to produce the temperature dependent biasvoltage.
 41. The method of claim 40 additionally comprising the steps ofgenerating a plurality of voltage drops across two terminals of aplurality of transistors representative of the transistors in the memorycell with said temperature dependent constant current, and averagingsaid voltage drops before said amplifying step.
 42. A method,comprising: generating a temperature dependent constant current;generating a fixed constant current; selecting one of said temperaturedependent and fixed constant currents; generating a plurality of voltagedrops representative of the voltage drops across the gate and sourceterminals of access transistors in a loadless, four transistor cellusing said selected constant current; averaging said voltage drops toproduce an average voltage; and applying said average voltage to thegate terminals of the access transistors.